1. Field of the Invention
The invention relates in general to an electrode structure of an infrared detector, and more particularly, to an electrode structure of a hetero-junction internal photo-emission (HIP) infrared detector.
2. Description of the Related Art
As the development of military science and radiotelemetry technique become more and more advanced, the application by employing an infrared focal array (FPA) is more and more important. An intensive research has been directed towards the infrared detector with a wavelength of about 8 .mu.m to 14 .mu.m due to its high sensitivity against the object temperature nearby.
In Appl. Phys. Lett., 1990, 57(14), T. L. Lin and J. Maserjian have disclosed a p.sup.+-Ge.sub.x Si.sub.1-x /p-Si HIP infrared detector as shown in FIG. 1. The detector comprises a p-type silicon substrate 100. In the p-type substrate 100, a p.sup.+ contact 102 for Ohmic contact and an n.sup.+ guard ring 104 are formed. A silicon oxide layer 106 is formed and defined on the p-type silicon substrate 100. As shown in the figure, a central part of the p.sup.+ contact 102, an inner part of the guard ring 104, and a region 108 of the p.sup.+ silicon substrate 100 which is encompassed by the guard ring 104 are exposed. A p.sup.+ -Ge.sub.x Si.sub.1-x /p-Si layer 110 is formed on the exposed guard ring 104 and the exposed p.sup.+ silicon substrate 100. An aluminum layer is formed and defined. Therefore, an aluminum (Al) electrode 112a covers the exposed p.sup.+ contact 102 and a part of the silicon oxide layer 106. Another Al electrode 112b is formed on a part of the p.sup.+ -Ge.sub.x Si.sub.1-x /p-Si layer 110 at a region aligned over the silicon oxide layer 106.
In the above structure, since the aluminum electrode 112b does not directly contact with the silicon substrate 100, therefore, the spike effect between aluminum and silicon is avoided. As a consequence, the leakage current is reduced and suppressed. However, there are two drawbacks of the structure:
1) The thickness of the Ge.sub.x Si.sub.1-x layer is as thin as about 100 nm, so that the silicon oxide layer 106 as an insulation has to be as thin as possible to avoid the Ge.sub.x Si.sub.1-x layer to break in the step region. However, considering the dielectric property, the silicon oxide layer has to maintain a certain thickness. Furthermore, while cleaning the Ge.sub.x Si.sub.1-x layer during patterning, a part of the silicon oxide layer is removed by the cleaning solution, for example, HF. Therefore, a very high manufacturing cost is required to control the thickness of the silicon oxide layer during cleaning process for the Ge.sub.x Si.sub.1-x layer and growing process of silicon oxide layer. PA0 2) The region of the Ge.sub.x Si.sub.1-x layer over the silicon oxide layer is in an amorphous state. Therefore, a poor conductivity is obtained, and a parasitic resistance is formed to affect the performance of the device.